juicebox_asm/insn/
add.rs

1// SPDX-License-Identifier: MIT
2//
3// Copyright (c) 2023, Johannes Stoelp <dev@memzero.de>
4
5use super::Add;
6use crate::{Asm, Imm16, Imm32, Imm8, Mem16, Mem32, Mem64, Mem8, Reg16, Reg32, Reg64};
7
8impl Add<Reg32, Reg32> for Asm {
9    fn add(&mut self, op1: Reg32, op2: Reg32) {
10        self.encode_rr_mr(&[0x01], op1, op2);
11    }
12}
13
14impl Add<Reg64, Reg64> for Asm {
15    fn add(&mut self, op1: Reg64, op2: Reg64) {
16        self.encode_rr_mr(&[0x01], op1, op2);
17    }
18}
19
20impl Add<Reg32, Imm32> for Asm {
21    fn add(&mut self, op1: Reg32, op2: Imm32) {
22        self.encode_ri(0x81, 0, op1, op2);
23    }
24}
25
26impl Add<Reg64, Imm32> for Asm {
27    fn add(&mut self, op1: Reg64, op2: Imm32) {
28        self.encode_ri(0x81, 0, op1, op2);
29    }
30}
31
32impl Add<Mem16, Reg16> for Asm {
33    fn add(&mut self, op1: Mem16, op2: Reg16) {
34        self.encode_mr(&[0x01], op1, op2);
35    }
36}
37
38impl Add<Mem32, Reg32> for Asm {
39    fn add(&mut self, op1: Mem32, op2: Reg32) {
40        self.encode_mr(&[0x01], op1, op2);
41    }
42}
43
44impl Add<Mem64, Reg64> for Asm {
45    fn add(&mut self, op1: Mem64, op2: Reg64) {
46        self.encode_mr(&[0x01], op1, op2);
47    }
48}
49
50impl Add<Reg32, Mem32> for Asm {
51    fn add(&mut self, op1: Reg32, op2: Mem32) {
52        self.encode_rm(&[0x03], op1, op2);
53    }
54}
55
56impl Add<Reg64, Mem64> for Asm {
57    fn add(&mut self, op1: Reg64, op2: Mem64) {
58        self.encode_rm(&[0x03], op1, op2);
59    }
60}
61
62impl Add<Mem8, Imm8> for Asm {
63    fn add(&mut self, op1: Mem8, op2: Imm8) {
64        self.encode_mi(0x80, 0, op1, op2);
65    }
66}
67
68impl Add<Mem16, Imm8> for Asm {
69    fn add(&mut self, op1: Mem16, op2: Imm8) {
70        self.encode_mi(0x83, 0, op1, op2);
71    }
72}
73
74impl Add<Mem32, Imm8> for Asm {
75    fn add(&mut self, op1: Mem32, op2: Imm8) {
76        self.encode_mi(0x83, 0, op1, op2);
77    }
78}
79
80impl Add<Mem64, Imm8> for Asm {
81    fn add(&mut self, op1: Mem64, op2: Imm8) {
82        self.encode_mi(0x83, 0, op1, op2);
83    }
84}
85
86impl Add<Mem16, Imm16> for Asm {
87    fn add(&mut self, op1: Mem16, op2: Imm16) {
88        self.encode_mi(0x81, 0, op1, op2);
89    }
90}
juicebox_asm/insn/add.rs

juicebox_asm/insn/
add.rs
